/**************************************************************
   External ROM Access Module for "FPGA Xevious"

      Written by Tsuyoshi HASEGAWA <t-haseg@lares.dti.ne.jp>
***************************************************************/
module XEVIOUS_EROMAXS(

   input         AXSCLK,      // Max. 25MHz

   output [17:0] ROMADRS,
   input  [15:0] ROMD,

   input  [11:0] BGCH_A,      // BG Chip ROM address
   input  [14:0] SPCH_A,      // Sprite Chip ROM address
   input  [13:0] MCPU_A,      // Main CPU Inst.ROM address
   input  [12:0] SCPU_A,      // Sub CPU Inst.ROM address
   input  [16:0] EPCM_A,      // Explode Sound PCMdata address
   input  [12:0] PMP0_A,      // Planet Mapdata ROM0 address
   input  [12:0] PMP1_A,      // Planet Mapdata ROM1 address

   output [15:0] BGCH_D,
   output [15:0] SPCH_D,
   output  [7:0] MCPU_D,
   output  [7:0] SCPU_D,
   output  [7:0] EPCM_D,
   output [15:0] PMP0_D,
   output  [7:0] PMP1_D,

   output  [3:0] PHASE

);

reg    [3:0]   CLKS;

reg   [17:0]   ROMA;

reg   [15:0]   BGCH_DT;
reg   [15:0]   SPCH_DT;

reg   [15:0]   MCPU_DT;
reg   [15:0]   SCPU_DT;

reg   [15:0]   EPCM_DT;

reg   [15:0]   PMP0_DT;
reg   [15:0]   PMP1_DT;


assign   ROMADRS = ROMA;
assign   PHASE   = CLKS;

assign   BGCH_D  = BGCH_DT;
assign   SPCH_D  = SPCH_DT;

assign   MCPU_D  = MCPU_A[0] ? MCPU_DT[15:8] : MCPU_DT[7:0];
assign   SCPU_D  = SCPU_A[0] ? SCPU_DT[15:8] : SCPU_DT[7:0];

assign   EPCM_D  = EPCM_A[0] ? EPCM_DT[15:8] : EPCM_DT[7:0];

assign   PMP0_D  = PMP0_DT;
assign   PMP1_D  = PMP1_A[0] ? PMP1_DT[15:8] : PMP1_DT[7:0];


/*
XEVIOUS_ROM_IMAGE(word_address)
-------------------------------------
               BG_CHIP - $00000000
-------------------------------------
              MAIN_CPU - $00001000
               SUB_CPU - $00003000
-------------------------------------
               SP_CHIP - $00004000
-------------------------------------
      PLANET_MAP_2A&2B - $00009000
         PLANET_MAP_2C - $0000B000
-------------------------------------
      TARGET_EXP(9846) - $0000B800
     MYSHIP_EXP(17952) - $0000CB40
-------------------------------------
        DEBUG_RAMIMAGE - $0000EE58
-------------------------------------
          TOTAL(bytes) - $000234C0
*/

wire  [17:0]   bgrom_a  =             BGCH_A;
wire  [17:0]   sprom_a  = 18'h04000 + SPCH_A;

wire  [17:0]   mrom_a   = 18'h01000 + MCPU_A[13:1];
wire  [17:0]   srom_a   = 18'h03000 | SCPU_A[12:1];

wire  [17:0]   pm0rom_a = 18'h09000 + PMP0_A;
wire  [17:0]   pm1rom_a = 18'h0B000 + PMP1_A[12:1];

`ifdef VIDEO_DEBUG
wire  [17:0]   pcmrom_a = 18'h0EE58 + EPCM_A[16:1]; // DEBUG_RAMIMAGE
`else
wire  [17:0]   pcmrom_a = 18'h0B800 + EPCM_A[16:1];
`endif

always @ ( negedge AXSCLK ) begin

   CLKS <= CLKS+1;

   case ( CLKS )

   4'h0: begin PMP1_DT <= ROMD; ROMA <=  sprom_a; end
   4'h1: begin SPCH_DT <= ROMD; ROMA <=  bgrom_a; end
   4'h2: begin BGCH_DT <= ROMD; ROMA <=   mrom_a; end
   4'h3: begin MCPU_DT <= ROMD; ROMA <=   srom_a; end

   4'h4: begin SCPU_DT <= ROMD; ROMA <=  sprom_a; end
   4'h5: begin SPCH_DT <= ROMD; ROMA <=  bgrom_a; end
   4'h6: begin BGCH_DT <= ROMD; ROMA <= pm0rom_a; end
   4'h7: begin PMP0_DT <= ROMD; ROMA <= pm1rom_a; end

   4'h8: begin PMP1_DT <= ROMD; ROMA <=  sprom_a; end
   4'h9: begin SPCH_DT <= ROMD; ROMA <=  bgrom_a; end
   4'hA: begin BGCH_DT <= ROMD; ROMA <=   mrom_a; end
   4'hB: begin MCPU_DT <= ROMD; ROMA <=   srom_a; end

   4'hC: begin SCPU_DT <= ROMD; ROMA <=  sprom_a; end
   4'hD: begin SPCH_DT <= ROMD; ROMA <=  bgrom_a; end
   4'hE: begin BGCH_DT <= ROMD; ROMA <= pcmrom_a; end
   4'hF: begin EPCM_DT <= ROMD; ROMA <= pm1rom_a; end

   endcase

end

endmodule