--- rx.md.bitmem	2012-06-27 22:05:19.000000000 +0900
+++ rx.md	2012-12-19 20:17:41.745650509 +0900
@@ -1977,6 +1977,64 @@
    (set_attr "timings" "33")]
 )
 
+(define_insn "*bitset_in_memory_little"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+       (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
+                          (match_operand:QI 1 "const_int_operand" "i")) 0))]
+  "exact_log2 (INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bset\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
+(define_insn "*bitset_in_memory_big"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+       (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
+                          (match_operand:QI 1 "const_int_operand" "i")) 3))]
+  "exact_log2 (INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bset\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
+(define_insn "*bitset_in_memory_bitfiled"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+        (ior:QI (match_dup 0)
+                (match_operand:QI 1 "const_int_operand" "i")))]
+  "1/*!(MEM_VOLATILE_P (operands[0]) && flag_strict_volatile_bitfields)*/
+   && exact_log2 (INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bset\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
 (define_insn "*bitinvert"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(xor:SI (ashift:SI (const_int 1)
@@ -1998,6 +2056,64 @@
    (set_attr "timings" "33")]
 )
 
+(define_insn "*bitinvert_in_memory_little"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+       (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
+                          (match_operand:QI 1 "const_int_operand" "i")) 0))]
+  "exact_log2 (INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bnot\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
+(define_insn "*bitinvert_in_memory_big"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+       (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
+                          (match_operand:QI 1 "const_int_operand" "i")) 3))]
+  "exact_log2 (INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bnot\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
+(define_insn "*bitinvert_in_memory_bitfiled"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+        (xor:QI (match_dup 0)
+                (match_operand:QI 1 "const_int_operand" "i")))]
+  "1/*!(MEM_VOLATILE_P (operands[0]) && flag_strict_volatile_bitfields)*/
+   && exact_log2 (INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bnot\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
 (define_insn "*bitclr"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(and:SI (not:SI
@@ -2023,6 +2139,64 @@
    (set_attr "timings" "33")]
 )
 
+(define_insn "*bitclr_in_memory_little"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+       (subreg:QI (and:SI (subreg:SI (match_dup 0) 0)
+                          (match_operand 1 "const_int_operand" "i")) 0))]
+  "exact_log2 (~INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (~INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bclr\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
+(define_insn "*bitclr_in_memory_big"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "=Q")
+       (subreg:QI (and:SI (subreg:SI (match_dup 0) 0)
+                          (match_operand 1 "const_int_operand" "i")) 3))]
+  "exact_log2 (~INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (~INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bclr\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
+(define_insn "*bitclr_in_memory_bitfiled"
+  [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
+        (and:QI (match_dup 0)
+                (match_operand 1 "const_int_operand" "i")))]
+  "1/*!(MEM_VOLATILE_P (operands[0]) && flag_strict_volatile_bitfields)*/
+   && exact_log2 (~INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (~INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"bclr\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "length" "3")
+   (set_attr "timings" "33")]
+)
+
 (define_insn "*insv_imm"
   [(set (zero_extract:SI
 	  (match_operand:SI 0 "register_operand" "+r")