--- sh.md.gbr	2012-12-19 22:12:43.420260620 +0900
+++ sh.md	2012-12-21 20:30:13.408230422 +0900
@@ -3189,6 +3189,222 @@ label:
   "bclr\\t%W2,%0"
   [(set_attr "type" "arith")])
 
+(define_insn "*andqi_gbr_big"
+  [(set (mem:QI (match_operand:SI 0 "register_operand" "z"))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 0)) 0)
+                   (match_operand 1 "const_int_operand" "")) 3))
+  ]
+  "TARGET_SH1"
+  "and.b\\t%1,@(%0,gbr)"
+)
+
+(define_insn "*andqi_gbr_little"
+  [(set (mem:QI (match_operand:SI 0 "register_operand" "z"))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 0)) 0)
+                   (match_operand 1 "const_int_operand" "")) 0))
+  ]
+  "TARGET_SH1"
+  "and.b\\t%1,@(%0,gbr)"
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 2)
+        (and:SI (match_dup 2)
+                (match_dup 5)))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 2)
+        (and:SI (match_dup 2)
+                (match_dup 5)))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (and:SI (match_dup 2)
+                (match_operand 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (4, operands[0])
+   && peep2_reg_dead_p (4, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (and:SI (match_dup 2)
+                (match_operand 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (4, operands[0])
+   && peep2_reg_dead_p (4, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (and:SI (match_dup 5)
+                (match_dup 2)))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (5, R0_REG)
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+   && peep2_reg_dead_p (5, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (and:SI (match_dup 5)
+                (match_dup 2)))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (5, R0_REG)
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+   && peep2_reg_dead_p (5, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (and:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
 ;; If the constant is 255, then emit an extu.b instruction instead of an
 ;; and, since that will give better code.
 
@@ -3280,6 +3496,422 @@ label:
   "bset\\t%V2,%0"
   [(set_attr "type" "arith")])
 
+(define_insn "*iorqi_gbr_big"
+  [(set (mem:QI (match_operand:SI 0 "register_operand" "z"))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 0)) 0)
+                   (match_operand:QI 1 "const_int_operand" "")) 3))
+  ]
+  "TARGET_SH1 && TARGET_BITOPS"
+  "or.b\\t%1,@(%0,gbr)"
+)
+
+(define_insn "*iorqi_gbr_little"
+  [(set (mem:QI (match_operand:SI 0 "register_operand" "z"))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 0)) 0)
+                   (match_operand:QI 1 "const_int_operand" "")) 0))
+  ]
+  "TARGET_SH1 && TARGET_BITOPS"
+  "or.b\\t%1,@(%0,gbr)"
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_dup 5)))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_dup 5)))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (ior:SI (match_dup 5)
+                (match_dup 2)))
+   (set (match_dup 5)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (ior:SI (match_dup 5)
+                (match_dup 2)))
+   (set (match_dup 5)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && !(MEM_VOLATILE_P (operands[0]) && flag_strict_volatile_bitfields)
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (4, operands[0])
+   && peep2_reg_dead_p (4, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (ior:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && !(MEM_VOLATILE_P (operands[0]) && flag_strict_volatile_bitfields)
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (4, operands[0])
+   && peep2_reg_dead_p (4, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (ior:SI (match_dup 5)
+                (match_dup 2)))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && !(MEM_VOLATILE_P (operands[0]) && flag_strict_volatile_bitfields)
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+   && peep2_reg_dead_p (5, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (ior:SI (match_dup 5)
+                (match_dup 2)))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && !(MEM_VOLATILE_P (operands[0]) && flag_strict_volatile_bitfields)
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+   && peep2_reg_dead_p (5, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (ior:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "arith_reg_dest" "=r,r")
 	(ior:DI (match_operand:DI 1 "arith_reg_operand" "%r,r")
@@ -3373,6 +4005,418 @@ label:
 	xori	%1, %2, %0"
   [(set_attr "type" "arith_media")])
 
+(define_insn "*xorqi_gbr_big"
+  [(set (mem:QI (match_operand:SI 0 "register_operand" "z"))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 0)) 0)
+                   (match_operand:QI 1 "const_int_operand" "")) 3))
+  ]
+  "TARGET_SH1 && TARGET_BITOPS"
+  "xor.b\\t%1,@(%0,gbr)"
+)
+
+(define_insn "*xorqi_gbr_little"
+  [(set (mem:QI (match_operand:SI 0 "register_operand" "z"))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 0)) 0)
+                   (match_operand:QI 1 "const_int_operand" "")) 0))
+  ]
+  "TARGET_SH1 && TARGET_BITOPS"
+  "xor.b\\t%1,@(%0,gbr)"
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_dup 5)))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (sign_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_dup 5)))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (xor:SI (match_dup 5)
+                (match_dup 2)))
+   (set (match_dup 5)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (xor:SI (match_dup 5)
+                (match_dup 2)))
+   (set (match_dup 5)
+        (zero_extend:SI (match_operand:QI 3 "register_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_dup 3))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (6, R0_REG)
+   && peep2_reg_dead_p (6, operands[0])
+   && peep2_reg_dead_p (6, operands[2])
+   && peep2_reg_dead_p (6, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (4, operands[0])
+   && peep2_reg_dead_p (4, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_dup 2)
+        (xor:SI (match_dup 2)
+                (match_operand:QI 4 "const_int_operand" "")))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[2]) == REGNO (operands[3])
+   && REGNO (operands[2]) == R0_REG
+   && peep2_reg_dead_p (4, operands[0])
+   && peep2_reg_dead_p (4, operands[2])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (xor:SI (match_dup 5)
+                (match_dup 2)))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && !TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (5, R0_REG)
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+   && peep2_reg_dead_p (5, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 3))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
+(define_peephole2
+  [
+   (set (match_operand:SI 0 "register_operand" "")
+        (match_operand:SI 1 "general_operand" ""))
+   (set (match_operand:SI 2 "register_operand" "")
+        (sign_extend:SI (mem:QI (match_dup 0))))
+   (set (match_operand:SI 5 "register_operand" "")
+        (match_operand:SI 4 "const_int_operand" ""))
+   (set (match_dup 5)
+        (xor:SI (match_dup 5)
+                (match_dup 2)))
+   (set (mem:QI (match_dup 0))
+        (match_operand:QI 3 "register_operand" ""))
+  ]
+  "TARGET_SH1 && TARGET_LITTLE_ENDIAN && TARGET_BITOPS
+   && REGNO (operands[5]) == REGNO (operands[3])
+   && INTVAL (operands[4]) >= -128 && INTVAL (operands[4]) <= 127
+   && peep2_regno_dead_p (5, R0_REG)
+   && peep2_reg_dead_p (5, operands[0])
+   && peep2_reg_dead_p (5, operands[2])
+   && peep2_reg_dead_p (5, operands[5])
+  "
+  [
+   (set (match_dup 2)
+        (match_dup 1))
+   (set (mem:QI (match_dup 2))
+        (subreg:QI (xor:SI (subreg:SI (mem:QI (match_dup 2)) 0)
+                   (match_dup 4)) 0))
+  ]
+  "
+    operands[2] = gen_rtx_REG (SImode, R0_REG);
+  "
+)
+
 ;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
 ;; converts 2 * sign extend -> logical op into logical op -> sign extend
 (define_split