--- rx.md.bittst	2012-12-25 17:05:09.421313210 +0900
+++ rx.md	2012-12-30 22:22:11.179272447 +0900
@@ -240,6 +240,104 @@
   DONE;
 })
 
+(define_insn_and_split "*cbranchhi4_tst_ext"
+  [(set (pc)
+    (if_then_else
+      (match_operator 4 "rx_z_comparison_operator"
+        [ (if_then_else:SI
+               (zero_extract:SI
+           (subreg:SI
+                  (match_operand:HI 0 "register_operand" "r")
+                   0)
+           (match_operand    1 "rx_constshift_operand" "")
+           (match_operand    2 "rx_constshift_operand" ""))
+               (match_operand 5 "const_int_operand" "")
+               (const_int 0))
+         (const_int 0)])
+      (match_operand 3 "label_ref_operand" "")
+      (pc)))]
+  "INTVAL (operands[1]) == 1"
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  HOST_WIDE_INT mask;
+  rtx x;
+
+  mask = 1;
+  mask <<= INTVAL (operands[1]);
+  mask -= 1;
+  mask <<= INTVAL (operands[2]);
+
+  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
+
+  x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
+
+  rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
+            x, const0_rtx, operands[3]);
+  DONE;
+})
+
+(define_insn_and_split "*cbranchqi4_tst_ext"
+  [(set (pc)
+	(if_then_else
+	  (match_operator 4 "rx_z_comparison_operator"
+	    [ (if_then_else:SI 
+               (zero_extract:SI
+		   (subreg:SI 
+                  (match_operand:QI 0 "register_operand" "r")
+                   0)
+		   (match_operand    1 "rx_constshift_operand" "")
+		   (match_operand    2 "rx_constshift_operand" ""))
+               (match_operand 5 "const_int_operand" "")
+               (const_int 0))
+	     (const_int 0)])
+	  (match_operand 3 "label_ref_operand" "")
+	  (pc)))]
+  "INTVAL (operands[1]) == 1"
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  HOST_WIDE_INT mask;
+  rtx x;
+
+  mask = 1;
+  mask <<= INTVAL (operands[1]);
+  mask -= 1;
+  mask <<= INTVAL (operands[2]);
+
+  operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
+
+  x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
+
+  rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
+		    x, const0_rtx, operands[3]);
+  DONE;
+})
+
+(define_insn "*btstsi"
+  [(set (reg:CC_ZS CC_REG)
+        (compare:CC_ZS
+          (and:SI (match_operand:SI 0 "register_operand"  "r")
+                  (match_operand:SI 1 "const_int_operand" "i"))
+          (const_int 0)))]
+  "reload_completed
+   && exact_log2 (INTVAL (operands[1])) >= 0
+   && exact_log2 (INTVAL (operands[1])) <= 31"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1])));
+  output_asm_insn (\"btst\\t%1, %0\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "timings" "11")
+   (set_attr "length"  "3")]
+)
+
 (define_insn "*tstsi"
   [(set (reg:CC_ZS CC_REG)
 	(compare:CC_ZS
@@ -252,6 +350,118 @@
    (set_attr "length"  "3,7,6")]
 )
 
+(define_insn_and_split "*cbranchqi4_tst_ext_bitmem"
+  [(set (pc)
+	(if_then_else
+	  (match_operator 4 "rx_z_comparison_operator"
+	    [(zero_extract:SI
+		(match_operand:QI 0 "rx_restricted_mem_operand" "Q")
+		(match_operand    1 "rx_constshift_operand" "")
+		(match_operand    2 "rx_constshift_operand" ""))
+	     (const_int 0)])
+	  (match_operand 3 "label_ref_operand" "")
+	  (pc)))]
+  "INTVAL (operands[1]) == 1"
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  HOST_WIDE_INT mask;
+  rtx x;
+
+  mask = 1;
+  mask <<= INTVAL (operands[1]);
+  mask -= 1;
+  mask <<= INTVAL (operands[2]);
+  x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
+
+  rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
+		    x, const0_rtx, operands[3]);
+  DONE;
+})
+
+(define_insn_and_split "*cbranchqi4_tst_ext_mem"
+  [(set (pc)
+	(if_then_else
+	  (match_operator 4 "rx_z_comparison_operator"
+	    [ (if_then_else:SI 
+               (zero_extract:SI
+                 (match_operand:QI 0 "rx_restricted_mem_operand" "Q")
+		   (match_operand    1 "rx_constshift_operand" "")
+		   (match_operand    2 "rx_constshift_operand" ""))
+               (match_operand 5 "const_int_operand" "")
+               (const_int 0))
+	     (const_int 0)])
+	  (match_operand 3 "label_ref_operand" "")
+	  (pc)))]
+  "INTVAL (operands[1]) == 1"
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  HOST_WIDE_INT mask;
+  rtx x;
+
+  mask = 1;
+  mask <<= INTVAL (operands[1]);
+  mask -= 1;
+  mask <<= INTVAL (operands[2]);
+  x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
+
+  rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
+		    x, const0_rtx, operands[3]);
+  DONE;
+})
+
+(define_insn_and_split "*cbranchqi4_tst_ext_bitmem_msb"
+  [(set (pc)
+	(if_then_else
+	  (match_operator 2 "rx_zs_comparison_operator"
+	    [(subreg:SI
+		(match_operand:QI 0 "rx_restricted_mem_operand" "Q") 0)
+	     (const_int 0)])
+	  (match_operand 1 "label_ref_operand" "")
+	  (pc)))]
+  ""
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  rtx x;
+  enum rtx_code code;
+
+  x = gen_rtx_AND (SImode, operands[0], gen_int_mode (0x80, SImode));
+
+  code = GET_CODE (operands[2]);
+  if (code == GE) code = EQ;
+  if (code == LT) code = NE;
+  rx_split_cbranch (CC_ZSmode, code,
+		    x, const0_rtx, operands[1]);
+  DONE;
+})
+
+(define_insn "*tstqi_bitmem"
+  [(set (reg:CC_ZS CC_REG)
+	(compare:CC_ZS
+	  (and:SI (match_operand:QI 0 "rx_restricted_mem_operand"  "Q")
+		   (match_operand 1 "const_int_operand" ""))
+	  (const_int 0)))]
+  "reload_completed
+   && exact_log2 (INTVAL (operands[1]) & 0xff) >= 0
+   && exact_log2 (INTVAL (operands[1]) & 0xff) <= 7"
+  "*
+{
+  rtx xoperands[2];
+  xoperands[0] = operands[0];
+  xoperands[1] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
+  output_asm_insn (\"btst\\t%1, %0.B\", xoperands);
+  return \"\";
+}
+  "
+  [(set_attr "timings" "33")
+   (set_attr "length"  "3")]
+)
+
 (define_expand "cbranchsf4"
   [(set (pc)
 	(if_then_else